The present disclosure relates to transistor structures, and more specifically, to reducing gate resistance in multiple gate fin-type transistor structures.
Integrated circuit devices often include transistors that are useful in making and breaking electrical connections. One type of transistor utilizes one or more fins that extend from a substrate. The center of the fin usually makes up the channel region of the transistor and the outer ends of the fin make up the source and drain regions. A gate commonly passes over the central region of the fin, and controls the operation of transistor. Additional structures sometimes use multiple fins and multiple gates.
One issue that is encountered relates to the resistance of the gate conductor. Even 2-dimensional transistor devices experience gate conductor resistance related to the length or width of the gate conductor. However, because of the 3-dimensional nature of fin type transistors, the resistance of the gate conductor is even more pronounced, because the height of the gate conductor produces an additional resistance component.